A mobile communication terminal generally has two clocks, a high-frequency clock and a slow clock. The high-frequency clock is configured to realize timing control during an operating mode of the mobile communication terminal. The slow clock is configured to realize timing control during a standby mode of the mobile communication terminal, such that the mobile communication terminal can periodically awake from the standby mode to receive paging requests.
Referring to FIG. 1, a conventional clock circuit configured in a mobile communication terminal is illustrated. The clock circuit includes two crystals (which are respectively labeled as S1 and S2 in FIG. 1), and two oscillating circuits (which are respectively labeled as Z1 and Z2 in FIG. 1). The two crystals are independently used in different oscillating circuits (e.g. the crystal S1 is used in the oscillating circuit Z1, and the crystal S2 is used in the oscillating circuit Z2), for generating a high-frequency clock signal and a slow-clock signal, respectively. The clock circuit may further include a slow-clock calibration unit (which is labeled as J1 in FIG. 1). The slow-clock calibration unit J1 is adapted to realize slow-clock calibration by taking the high-frequency clock as a reference. Specifically, the slow-clock calibration unit J1 counts how many cycles the high-frequency clock has been through within a predetermined number of cycles of the slow clock, under circumstance that the two oscillating circuits (i.e. Z1 and Z2) are both on operation. As such, the slow clock can be calibrated with reference to the precise high frequency clock.
Currently, in some solutions, a modified clock circuit has been proposed in order to reduce product costs. The modified clock circuit includes only one crystal and correspondingly one oscillating circuit, plus a frequency divider F1, as shown in FIG. 2. Specifically, the frequency divider F1 is configured to divide a frequency output from the oscillating circuit Z1, thus obtaining a high-frequency clock signal when the mobile communication terminal is in the operating mode, and obtaining a slow-clock signal when the mobile communication terminal is in the standby mode. It can be seen that, the frequency divider F1 is unable to obtain the high-frequency clock signal and the slow-clock signal at the same time. As a result, the slow clock can not be calibrated by taking the high-frequency clock as a reference via the aforementioned way. Therefore, a solution of realizing slow-clock calibration is on the demand.